1. Technical Field
The present disclosure relates to a solid-state imaging device.
2. Description of the Related Art
A solid-state imaging device constituted by an MOS (Metal Oxide Semiconductor) image sensor has been known (see PTL 1). An MOS image sensor described in PTL 1 is hereinafter described with reference to FIG. 12.
FIG. 12 is a view illustrating a configuration of a conventional solid-state imaging device (MOS image sensor) described in PTL 1.
Conventional solid-state imaging device 400 illustrated in FIG. 12 includes pixel array unit 410, row selection circuit 420, horizontal transfer scanning circuit 430, timing control circuit 440, ADC (Analog-Digital Converter) group 450, ramp signal generator 460, amplifier circuit 470, signal processing circuit 480, and horizontal transfer line 490. ADC group 450 includes a plurality of single slope AD conversion circuits each of which contains comparator 451, counter 452, and latch circuit 453. Each of the single slope AD conversion circuits is provided for corresponding one of a plurality of vertical signal lines 454.
Pixel array unit 410 contains unit cells in matrix. Each of the unit cells contains a photoelectric conversion element and a unit-cell amplifier.
Timing control circuit 440, row selection circuit 420, and horizontal transfer scanning circuit 430 are control circuits provided to sequentially read pixel signals from pixel array unit 410. Signals corresponding to rows selected by row selection circuit 420 are collectively output to ADC group 450, where the signals generated as analog signals are converted into digital signals by ADC group 450 to generate digital data. The generated digital data is sequentially read by horizontal transfer scanning circuit 430 in the order of selection of columns to read all of pixel signals from pixel array unit 410. Timing control circuit 440 controls row selection circuit 420 and horizontal transfer scanning circuit 430 such that pixel signals can be sequentially read from pixel array unit 410.
ADC group 450 performs analog-digital conversion of pixel signals in a following manner.
Initially, comparator 451 executes comparison between reference voltage Vslope having a ramp waveform, which is a voltage generated by ramp signal generator 460 and varied stepwise with time, and a pixel signal obtained from the unit cell via vertical signal line 454. Counter 452 counts a comparison time of comparator 451. A counted result is output to latch circuit 453. A latched signal is output from amplifier circuit 470 via horizontal transfer line 490. Analog-digital conversion for a pixel signal is performed in this manner at ADC group 450.
According to the foregoing conventional solid-state imaging device, each of the comparators provided in the corresponding column compares a pixel signal in the corresponding column with a ramp signal (reference voltage Vslope) common to all the columns to perform collective analog-digital conversion for all the columns. When the ramp signal common to all the columns fluctuates by operation of the comparator in a certain column, this fluctuation is transmitted to the comparators in other columns. In this case, errors may be produced in the analog-digital conversion result.
For example, different analog-digital conversion results may be obtained in an area containing a bright portion and in an area not containing a bright portion for an identical input signal. This condition deteriorates image quality. In the following description, this phenomenon is referred to as streaking.